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Freescale Semiconductor Technical Data
MC33701 Rev 4.0, 05/2005
1.5 A Switch-Mode Power Supply with Linear Regulator
The 34701 provides the means to efficiently supply the Freescale Power QUICCTM I, II, and other families of Freescale microprocessors and DSPs. The 34701 incorporates a highperformance switching regulator, providing the direct supply for the microprocessor's core, and a low dropout (LDO) linear regulator control circuit providing the microprocessor I/O and bus voltage. The switching regulator is a high-efficiency synchronous buck regulator with integrated N-channel power MOSFETs to provide protection features and to allow space-efficient, compact design. The 34701 incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. Features * * * * * * * * * Operating Voltage from 2.8 V to 6.0 V High-Accuracy Output Voltages Fast Transient Response Switcher Output Current Up to 1.5 A Undervoltage Lockout and Overcurrent Protection Enable Inputs and Programmable Watchdog Timer Voltage Margining via I2CTM Bus Reset with Programmable Power-ON Delay Pb-Free Packaging Designated by Suffix Code EK
I2C is a trademark of Philips Corporation.
34701
POWER SUPPLY INTEGRATED CIRCUIT
EK (Pb-FREE) SUFFIX 98AARH99137A 32-TERMINAL SOICW
ORDERING INFORMATION
Device MC34701EK/R2 Temperature Range (TA) -40 to 85C Package 32 SOICW
2.8 V to 6.0 V Input
34701
VIN2 VBD VBST RT VIN1 LDRV CS LDO LFB MPC8xxx RST BOOT SW VOUT PGND INV VDDI VBST Adjustable: 0.8 V to VIN Dropout PORESET Other Circuits Adjustable: 0.8 V to VIN Dropout VDDH (I/Os)
ADDR SDA SCL GND EN1 EN2 CLKSYN CLKSEL Optional FREQ
VDDL (Core)
Figure 1. 34701 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIN1
VIN VDDI Internal Supply 8.0 V VDDI VDDI VBST Power Enable VDDI Bandgap Voltage Reference VDDI VLDO Power Sequencing Reset Q6 Reset Control POR Timer SysCon INV LFB C Control I2 Voltage Margining VOUT Watchdog Timer Current Limit VDDI Buck HS and LS Driver Q1 VIN2 (2) VBST BOOT Power Down Power Seq UVLO Q4 VDDI Linear Regulator Control ILim LFB LCMP To Reset Control LDRV CS
VBST
VBST
VBD Q5 Boost Control VREF VREF
EN1 EN2 RST
RT
I2C Control
Thermal Limit
ADDR SDA SCL Switcher Oscillator 300 kHz Ramp Gen. I2C Interface PWM Comp Error Amp
CLKSEL
CLKSYN FREQ
Figure 2. 34701 Simplified Internal Block Diagram
34701
2
+
VREF
-
LDO
VREF
VBST
SysCon SoftSt
Buck Control Logic
SW (2) Q2 PGND (2)
+
+
0.8 V
To Reset Control INV VOUT VOUT Q3
-
-
Power Seq GND (4)
Analog Integrated Circuit Device Data Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
FREQ INV VOUT VIN2 VIN2 SW SW GND GND PGND PGND VBD VBST BOOT SDA SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CLKSYN CLKSEL
RST
RT EN2 EN1 ADDR GND GND VDD1 VIN1 LDRV CS LDO LFB LCMP
Figure 3. Terminal Connections Table 1. Terminal Function Description
A functional description of each terminal can be found in the FUNCTIONAL TERMINAL DESCRIPTION section beginning on page 15.
Terminal 1 Terminal Name FREQ Formal Name Oscillator Frequency Definition This switcher frequency selection terminal can be adjusted by connecting external resistor RF to the FREQ terminal. The default switching frequency (FREQ terminal left open or tied to VDDI) is set to 300 kHz. Buck Controller Error Amplifier inverting input. Output voltage of the buck converter. Input terminal of the switching regulator power sequence control circuit. Buck regulator power input. Drain of the high-side power MOSFET. Buck regulator switching node. This terminal is connected to the inductor. Analog ground of the IC, thermal heatsinking. Buck regulator power ground. Drain of the internal boost regulator power MOSFET. Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST terminal is 7.75V nominal. Bootstrap capacitor input. I2C bus terminal. Serial data. I2C bus terminal. Serial clock. Linear regulator compensation terminal. Linear regulator feedback terminal. Input terminal of the linear regulator power sequence control circuit.
2 3 4, 5 6, 7 8, 9 24, 25 10, 11 12 13
INV VOUT VIN2 SW GND PGND VBD VBST
Inverting Input Output Voltage Input Voltage 2 Switch Ground Power Ground Boost Drain Boost Voltage
14 15 16 17 18 19
BOOT SDA SCL LCMP LFB LDO
Bootstrap Serial Data Serial Clock Linear Compensation Linear Feedback Linear Regulator
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
3
TERMINAL CONNECTIONS
Table 1.
Terminal Function Description (continued)
A functional description of each terminal can be found in the FUNCTIONAL TERMINAL DESCRIPTION section beginning on page 15.
Terminal 20 Terminal Name CS Formal Name Current Sense Definition Current sense terminal of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO terminals. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. LDO gate drive of the external pass N-channel MOSFET. The input supply terminal for the integrated circuit. The internal circuits of the IC are supplied through this terminal. Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is recommended. I2C address selection. This terminal can either be left open, tied to VDDI, or grounded through a 10 k resistor. Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determines operation mode and type of power sequencing of the IC. Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determines operation mode and type of power sequencing of the IC. This terminal allows programming of the Power-ON Reset delay by means of an external RC network. The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. This terminal sets the CLKSYN terminal as either an oscillator output or a synchronization input terminal. The CLKSEL terminal is also used for the I2C address selection. Oscillator output/synchronization input terminal.
21 22 23 26 27 28 29 30
LDRV VIN1 VDDI ADDR EN1 EN2 RT
RST
Linear Drive Input Voltage 1 Power Supply Address Enable 1 Enable 2 Reset Timer Reset Output (Active LOW) Clock Selection
31
CLKSEL
32
CLKSYN
Clock Synchronization
34701
4
Analog Integrated Circuit Device Data Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating Electrical Ratings Supply Voltage Switching Node Voltage Buck Regulator Bootstrap Input Voltage (BOOT - SW) Boost Regulator Output Voltage Boost Regulator Drain Voltage
RST Drain Voltage
Symbol
Value
Unit
VIN1, VIN2 VSW VIN(BOOT) VBST VBD VRST
-0.3 to 7.0 -1.0 to 7.0 -0.3 to 8.5 -0.3 to 8.5 -0.3 to 9.5 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0
V V V V V V V V V
Enable Terminal Voltage at EN1, EN2 Logic Terminal Voltage at SDA, SCL Analog Terminal Voltage LDO, VOUT, RST LDRV, LCMP, CS Terminal Voltage at CLKSEL, ADDR, RT, FREQ, VDDI, CLKSYN, INV, LFB ESD Voltage (1) Human Body Model Machine Model Thermal Ratings Storage Temperature Lead Soldering Temperature (2) Maximum Junction Temperature Thermal Resistance Junction to Ambient (Single Layer)
(3) (4)
VEN VLOG VOUT VLIN VLOGIC
-0.3 to 7.0 -0.3 to 8.5 -0.3 to 3.6 V V
VESD
2000 200
TSTG TSOLDER TJMAX RJA ,
-65 to 150 260 125
C C C C/W
70 55 RJB TA 18 -40 to 85 C/W C
Junction to Ambient (Four Layers) (3), (4) Thermal Resistance, Junction to Base (5) Operational Package Temperature (Ambient Temperature)
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP=200 pF, RZAP=0 ), and the Charge Device Model. 2. Lead soldering temperature limit is for 10 seconds maximum duration. 3. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance. 4. Per JEDEC JESD51-6 with the board horizontal 5. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted.
Characteristic General Operating Voltage Range (VIN1, VIN2) Start-Up Voltage Threshold (Boost Switching) VBST Undervoltage Lockout (VBST rising) VBST Undervoltage Lockout Hysteresis Input DC Supply Current (Normal Operation Mode, Enabled), Unloaded Outputs VIN1 Terminal Input Supply Current (EN1 = EN2 = 0) VIN2 Terminal Input Leakage Current (EN1 = EN2 = 0) VDDI Internal Supply Voltage VDDI Maximum Output Current (Externally Loaded) Buck Converter Buck Converter Feedback Voltage (6), (7) IVOUT = 15 mA to 1.5 A. Includes Load Regulation Error Buck Converter Voltage Margining Step Size Buck Converter Voltage Margining Highest Positive Value Buck Converter Voltage Margining Lowest Negative Value Buck Converter Line Regulation
(6), (7)
Symbol
Min
Typ
Max
Unit
VIN VST VBST_UVLO VBST_UVLO_HYS IIN IIN1 IIN2 VDDI IDDI
2.8 - 5.5 0.5 - - - 2.9 -
- 1.6 - - 60 10 100 - -
6.0 1.8 6.5 1.5 - - - 3.3 -10
V V V V mA mA A V mA
VINV 0.784 VMVO VMP VMN REGLNVO -1.0 REGLDVO -1.0 IINVOUT - IININV -1.0 3.5 - - 1.0 - 1.0 - 1.0 - 5.9 -7.9 0.800 1.0 - - 0.816 - 7.9 -5.9
V
% % % %
VIN1 = VIN2 = 2.8 V to 6.0 V, IVOUT = 15 mA to 1.5 A Buck Converter Load Regulation (6), (7) VIN1 = VIN2 = 2.8 V to 6.0 V, IVOUT = 15 mA to 1.5 A VOUT Input Leakage Current VOUT = 5.25 V INV Input Leakage Current INV = 0.8 V Notes 6. Design information only. This parameter is not production tested. 7. IVOUT refers to load current on output switcher.
%
mA
A
34701
6
Analog Integrated Circuit Device Data Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted.
Characteristic Buck Converter (continued) High-Side Power MOSFET Q1 RDS(ON) (8), (9) ID = 500 mA, TA = 25C, VBST = 8.0 V Low-Side Power MOSFET Q2 RDS(ON) (8), (9) ID = 500 mA, TA = 25C, VBST = 8.0 V Buck Converter Peak Current Limit (High Level) VOUT Pulldown MOSFET Q3 Current Limit TA = 25C, VBST = 8.0 V VOUT Pulldown MOSFET Q3 RDS(ON)(9) ID = 1.0 A, VBST = 8.0 V Thermal Shutdown (VOUT Pulldown MOSFET Q3) (8) Thermal Shutdown Hysteresis (8) Notes 8. Design information only. This parameter is not production tested. 9. ID is the MOSFET drain current. TSD THYS RDS(ON)PQ3 - 150 - - 170 10 1.9 190 - C C ILIMH ILIMPQ3 0.75 - 2.0 RDS(ON)Q2 - -4.0 65 -2.7 - -1.5 A A RDS(ON)Q1 - 60 - m m Symbol Min Typ Max Unit
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
7
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted.
Characteristic Error Amplifier (Buck Converter) Input Impedance (10) Output Impedance (10) DC Open Loop Gain
(10)
Symbol
Min
Typ
Max
Unit
RIN ROUT AVOL GBW vSR V EA_OH
- - - - -
500 150 80 35 200
- - - - -
k dB MHz V/s V
Gain Bandwidth Product (10) Slew Rate
(10)
Output Voltage - High Level VIN1 > 3.3 V, IOEA = -1.0 mA (10), (11) Output Voltage - Low Level IOEA = -1.0 mA (10), (11) Oscillator Ramp (10) Oscillator CLKSYN Terminal (open) Low Level Output Voltage IOL = +1.0 mA
(12)
- V EA_OL - VSCRamp -
2.0
- V
0.4 0.5
- - V
VOSC_OL
-
-
0.4
V
CLKSYN Terminal (open) High Level Output Voltage IOH = -1.0 mA
(13)
VOSC_OH
VDDI - 0.4 V - - - 1.26 - 2.0 240 -
V
CLKSYN Terminal (grounded) Input Voltage Threshold CLKSYN Terminal Pullup Resistance Frequency Adjusting Reference Voltage Boost Regulator Regulator Output Voltage IBST = 20 mA, VIN1 = VIN2 = 2.8 V to 6.0 V Power MOSFET Q5 RDS(ON) IBD = 500 mA, TA = 25C Regulator Recommended Output Capacitor Regulator Recommended Output Capacitor Maximum ESR Notes 10. 11. 12. 13. Design information only. This parameter is not production tested. IOEA Refers to Error Amplifier Output Current. IOL Refers to I/O Low Level IOH Refers to I/O High Level
(10)
VOSC_IH RPU VFREQ
1.2 60 -
V k V
VBST 7.3 RDS(ON)Q5 - CBST ESRCBST - - 650 10 100 1000 - - 7.7 8.3
V
m
F m
34701
8
Analog Integrated Circuit Device Data Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted.
Characteristic Linear Regulator (LDO) LDO Feedback Voltage (15) VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA. Includes Load Regulation Error LDO Voltage Margining Step Size LDO Voltage Margining Highest Positive Value LDO Voltage Margining Lowest Negative Value LDO Line Regulation (15) VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 1000 mA LDO Load Regulation (15) ILDO = 10 mA to 1000 mA LDO Ripple Rejection, Dropout Voltage VDO = 1.0 V, VRIPPLE = +1.0 V p-p Sinusoidal, f = 300 kHz, ILDO = 500 mA (14) LDO Maximum Dropout Voltage (VIN - VLDO), using IRL2703 (15) VLDO = 2.5 V, ILDO = 1000 mA LDO Current Sense Comparator Threshold Voltage (VCS - VLDO) LDO Terminal Input Current, VLDO = 5.25 V LDO Feedback Input Current (LFB Terminal), VLFB = 0.8 V LDO Drive Output Current (LDRV Terminal), VLDRV = 0 V CS Terminal Input Leakage Current VCS = 5.25 V LDO Pulldown MOSFET Q4 Current Limit TA = 25C, VBST = 8.0 V (LDO Terminal) LDO Pulldown MOSFET Q4 RDS(ON) ID = 1.0 A, VBST = 8.0 V LDO Recommended Output Capacitance LDO Recommended Output Capacitor ESR Thermal Shutdown (LDO Pulldown MOSFET Q4) (14) Thermal Shutdown Hysteresis (14) CLDO RLDO TSD TSDHYS RDS(ON)Q4 - - - 150 - - 10 5.0 170 10 1.9 - - 190 - F m C C I LIMQ4 0.75 - 2.0 VCSTH I LDO I LFB I LDRV I CSLK 50 - 200 A VDO - 35 1.0 -1.0 -5.0 50 50 1.9 - -3.3 75 65 4.0 1.0 -2.0 mV mA A mA A mV
(15)
Symbol
Min
Typ
Max
Unit
V LFB 0.784 V MLDO V MP V MN REGLNVLDO -1.0 REGLDVLDO -1.0 VLDO_RR - 40 - - 1.0 - 1.0 - 5.9 -7.9 0.800 1.0 - - 0.816 - 7.9 -5.9
V
% % % %
%
dB
Notes 14. Design information only. This parameter is not production tested. 15. IDO refers to Load Current on External LDOFET - IRL2703 is the Intersil MOSFET.
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
9
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted.
Characteristic Control and Supervisory Circuits Enable (EN1, EN2) Input Voltage Threshold Enable (EN1, EN2) Pulldown Resistance
RST Low-Level Output Voltage, IOL = 5.0 mA RST Leakage Current, OFF State, Pulled Up to 5.25 V RST Undervoltage Threshold on VOUT (VOUT/VOUT)
(16)
Symbol
Min
Typ
Max
Unit
VEN-TH REN-PD VOL ILKG-RST VOUTITh VOUTITh VLDOITh VLDOITh VTH-RT IS-RT I LKG-RT V SAT-RT Ct VTHCLKS RPU-CLKS VTHADDR RPU-ADDR TLIM TLIMHYS
1.0 30 - - -14 0.5 -12 4.0 1.0 -17 -1.0 - - 1.2 60 1.2 60 150 -
1.5 55 - - - - - - 1.2 - - 35 - 1.6 120 1.6 120 170 10
2.0 90 0.4 10 -0.5 14 -4.0 12 1.5 -34 1.0 100 47 2.0 240 2.0 240 190 -
V k V A % % % % V mA A mV F V k V k C C
RST Overvoltage Threshold on VOUT (VOUT/VOUT) (16) RST Undervoltage Threshold on VLDO (VLDO/VLDO) (16) RST Overvoltage Threshold on VLDO (VLDO/VLDO) RST Timer Voltage Threshold RST Timer Source Current (RT terminal at 0 V) RST Timer Leakage Current RST Timer Saturation Voltage, Reset Timer Current = 300 A
(16)
Maximum Recommended Value of the Reset Timer Capacitor CLKSEL Threshold Voltage CLKSEL Pullup Resistance ADDR Threshold Voltage (16) ADDR Pullup Resistance Thermal Shutdown (IC sensor) (16) Thermal Shutdown Hysteresis
(16)
SDA, SCL Terminals I2C Bus (Standard) Input Threshold Voltage (Terminal SCL), Rising Edge (16) Input Threshold Voltage (Terminal SDA) SDA, SCL Input Current, Input Voltage = 5.25 V (VIN1) SDA Low-Level Output Voltage, 3.0 mA Sink Current SDA, SCL Capacitance
(16)
VLTH VLTH IIN VOL CInput
1.3 1.3 - - -
- - 1.0 - 7.0
1.7 1.7 10 0.4 10
V V A V pF
Notes 16. Design information only. This parameter is not production tested.
34701
10
Analog Integrated Circuit Device Data Freescale Semiconductor
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figures 33) unless otherwise noted.
Characteristic Buck Converter Duty Cycle Range (Normal Operation) (17) Switching Node SW Rise Time (17) VIN = 5.0 V, ILOAD = 1.0 A Switching Node SW Fall Time (17) VIN = 5.0 V, ILOAD = 1.0 A Maximum Deadtime (17) Buck Control Loop Propagation Delay (17) VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10% of Low Level Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1) (17) Fault Condition Time-Out (17) Retry Timer Cycle (17) Oscillator Oscillator Center Frequency(19) RF = 11.3 k Oscillator Frequency Range Oscillator Frequency Adjusting Resistor Range Oscillator Frequency Adjustment (18), (19) RF = 7.0 k Oscillator Frequency Adjustment RF = 22 k Oscillator Default Frequency (Switching Frequency), FREQ Terminal Open Oscillator Output Signal Duty Cycle (Square Wave, 180 Out-of-Phase with the Internal Suitable Oscillator) Synchronization Pulse Minimum Duration (17) Notes 17. Design information only. This parameter is not production tested. 18. see Figure 4 for more details 19. RF is RFREQ fOSC DOSC tSYNC
(18), (19)
Symbol
Min
Typ
Max
Unit
tD tRISE
0
-
95
% ns
- tFALL - tD tPD - tSS tFAULT tRET 200 7.0 70 -
7.0
- ns
17 35
- - ns ns
50 350 10 100
- 800 15 150 s ms ms
fOSC
270
300
330
kHz
fOSC RFREQ fOSC
200 7.0
- -
400 22
kHz k kHz
400 fOSC - - 40 1.0
-
- kHz
- 300 50 -
200 - 60 - s kHz %
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
11
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figures 33) unless otherwise noted.
Characteristic Boost Regulator Boost Regulator MOSFET Maximum ON Time (20) Boost Regulator Control Loop Propagation Delay (20) Boost Switching Node VBD Rise Time IBST = 20 mA Boost Switching Node VBD Fall Time (20) IBST = 20 mA Linear Regulator (LDO) Fault Condition Time-Out Retry Timer Cycle Reset Monitor (RST) Monitoring LFB Terminal Delay Monitoring INV Terminal Delay SCA, SCL Terminal, I2C Bus (Standard) SCL Clock Frequency (20) Bus Free Time Between a STOP and a START Condition (20) Hold Time (Repeated) START Condition (After this period, the first clock pulse is generated.) (20) Low Period of the SCL Clock (20) High Period of the SCL Clock (20) SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF, 3.0 mA Sink Current (20), (22) Setup Time for a Repeated START Condition (20) Data Hold Time for I2C Bus Devices (20), (21) Data Setup Time (20) Setup Time for STOP Condition (20) Capacitive Load for Each Bus Line (20) fSCL tBUF tHD-STA tLOW tHIGH tF tSU-STA tHD-DAT tSU-DAT tSU-STO CB - 4.7 - - 100 - kHz s s 4.0 4.7 4.0 - - - - - - s s ns - 4.7 0.0 250 4.0 - - - - - - - 250 - - - - 400 s s ns s pF tD_RST_LFB tD_RST_INV 12 12 - - 28 28 s s tFAULT tRet 7.0 70 10 100 15 150 ms ms tB_FALL - 3.0 -
(20)
Symbol
Min
Typ
Max
Unit
tON tBST_PD tB_RISE
- -
24 50
- -
s ns ns
-
5.0 ns
Notes 20. Design information only. This parameter is not production tested. 21. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 22. VIH is High Level Voltage on I2C bus lines and VIL is Low Level Voltage on I2C bus lines
34701
12
Analog Integrated Circuit Device Data Freescale Semiconductor
TIMING DIAGRAM
TIMING DIAGRAM
tHD-STA
tHD-STA tHD-DAT tSU-DAT
tSU-STA
tSU-STO
Figure 4. Definition of Time on the I2C Bus
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
13
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
300 300
3.00 Switcher ILIM (A) 2.80 2.60 2.40 2.20 2.00
-50 -50 0 50 0 50 Temperature (C) Temperature (C) Temperature (C) 100 100
fOSC (kHz) fOSC (kHz) Fosc (kHz) Fosc (kHz)
295 295 290 290 285 285 280 280
-50
0
50
100
Temperature (C)
Figure 8. Switcher ILim vs. Temperature
Figure 5. fOSC vs. Temperature
fOSC (kHz) Oscillator frequency (kHz)
450 400 300 250 200 150 100 7 12 Rf (kOhm Rf (k ) ) 17 22 350
0.83 0.82 0.81 0.80 0.79 0.78 0.77 -50 0 50 100
VREF (V) Vref (V)
Temperature (C) Te m pe rature(C)
Figure 6. fOSC vs. Rf
Figure 9. VREF vs. Temperature
1 00 90 80 70 60 50 40 30 20 1 0 0 0 0,5
Vin=3.3V, Vin=3.3V, Vin=5.0V, Vin=5.0V,
Vout=1.2V Vout=1.8V Vout=1.2V Vout=1.8V
1 1 ,5
25 23 21 19 17 15 13 11 9 7 5 0 100 200 300
RT (k ) with CT = = nF RT (kOhm) with CT 3333nF Figure 10. Timer (ms) vs. RT
Switcher Efficiency [%]
Load Current [A]
Figure 7. Switcher Efficiency vs. Load Current
34701
Timer (ms)
14
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34701 power supply integrated circuit provides the means to efficiently supply the Freescale Power QUICC and other families of Freescale microprocessors. It incorporates a high-performance synchronous buck regulator, supplying the microprocessor's core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. At the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system.
FUNCTIONAL TERMINAL DESCRIPTION OSCILLATOR FREQUENCY TERMINAL (FREQ)
This switcher frequency selection terminal can be adjusted by connecting external resistor RF to the FREQ terminal. The default switching frequency (FREQ terminal left open or tied to VDDI) is set to 300 kHz.
BOOTSTRAP TERMINAL (BOOT)
Bootstrap capacitor input.
SERIAL DATA TERMINAL (SDA)
I2C bus terminal. Serial data.
INVERTING INPUT TERMINAL (INV)
Buck Controller Error Amplifier inverting input.
SERIAL CLOCK TERMINAL (SCL)
I2C bus terminal. Serial clock.
OUTPUT VOLTAGE TERMINAL (VOUT)
Output voltage of the buck converter. Input terminal of the switching regulator power sequence control circuit.
LINEAR COMPENSATION TERMINAL (LCMP)
Linear regulator compensation terminal.
INPUT VOLTAGE 2 TERMINALS (VIN2)
Buck regulator power input. Drain of the high-side power MOSFET.
LINEAR FEEDBACK TERMINAL (LFB)
Linear regulator feedback terminal.
SWITCH TERMINALS (SW)
Buck regulator switching node. This terminal is connected to the inductor.
LINEAR REGULATOR TERMINAL (LDO)
Input terminal of the linear regulator power sequence control circuit.
GROUND TERMINALS (GND)
Analog ground of the IC, thermal heatsinking.
CURRENT SENSE TERMINAL (CS)
Current sense terminal of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO terminals. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS.
POWER GROUND TERMINALS (PGND)
Buck regulator power ground.
BOOST DRAIN TERMINAL (VBD)
Drain of the internal boost regulator power MOSFET.
LINEAR DRIVE TERMINAL (LDRV)
LDO gate drive of the external pass N-channel MOSFET.
BOOST VOLTAGE TERMINAL (VBST)
Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST terminal is 7.75V nominal.
INPUT VOLTAGE 1 TERMINAL (VIN1)
The input supply terminal for the integrated circuit. The internal circuits of the IC are supplied through this terminal.
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FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
POWER SUPPLY TERMINAL (VDDI)
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is recommended.
RESET TIMER TERMINAL (RT)
The Reset Timer power-up delay (RT) terminal is used to set the delay between the time when the LDO and switcher outputs are active and stable and the RST output is released. An external resistor and capacitor are used to program the timer. The power-up delay can be obtained by using the following formula: t D = 10 ms + R tC t Where R t is the Reset Timer programming resistor and C t is the Reset Timer programming capacitor, both connected in parallel from RT to ground. Note Observe the maximum C t value and expect reduced accuracy if R t is less than 10 k.
ADDRESS TERMINAL (ADDR)
The ADDR terminal is used to set the address of the device when used in an I2C communication. This terminal can either be tied to VDDI or grounded through a 10 k resistor. Refer to I2C Bus Operation on page 26 for more information on this terminal.
ENABLE 1 AND 2 TERMINALS (EN1 AND EN2)
These two terminals permit positive logic control of the Enable function and selection of the Power Sequencing mode concurrently. Table 5 depicts the EN1 and EN2 function and Power Sequencing mode selection. Both EN1 and EN2 terminals have internal pulldown resistors and both can withstand a short circuit to the supply voltage, 6.0 V.
Table 5.
EN1 0 0 1 1
RESET OUTPUT TERMINAL (RST)
The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. The Reset Control circuit supervises both output voltages--the linear regulator output VLDO and the switching regulator output VOUT. When either of these two regulators is out of regulation (high or low), the RST terminal is pulled low. There is a 20 s delay filter preventing erroneous resets. During power-up sequencing, RST is held low until the Reset Timer times out.
Operating Mode Selection
EN2 0 1 0 1 Operating Mode Regulators Disabled Standard Power Sequencing Inverted Power Sequencing No Power Sequencing, Regulators Enabled
CLOCK SELECTION TERMINAL (CLKSEL)
This terminal sets the CLKSYN terminal as either an oscillator output or a synchronization input terminal. The CLKSEL terminal is also used for the I2C address selection.
CLOCK SYNCHRONIZATION TERMINAL (CLKSYN)
Oscillator output/synchronization input terminal.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
The 34701 incorporates a high-performance synchronous buck regulator, supplying the microprocessor's core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system.
Boost Regulator
Power Sequencing Voltage Margining Watchdog Timer
UVLO
Buck Control Logic
I2C Interface
Reset Control POR Timer
Buck HS and LS Driver
VDDI Internal Supply
Bandgap Bandgap Voltage Voltage Reference Reference
Switcher Oscillator 300 kHz
Linear Regulator Control ILIM
Thermal Shutdown
Figure 11. 34701 Functional Internal Block Diagram
BOOST REGULATOR
A boost regulator provides a high voltage necessary to properly drive the buck regulator power MOSFETs, especially during the low input voltage condition. The LDO regulator external N-channel MOSFET gate is also powered from the boost regulator. In order to properly enhance the high-side MOSFETs when only a +3.3 V supply rail powers the integrated circuit, the boost regulator provides an output voltage of 7.75 V nominal value. The 34701 boost regulator uses a simple hysteretic current control technique, which allows fast power-up and does not require any compensation. When the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. After the inductor current reaches the upper current limit (nominally set at 1.0 A), the low-side switch is turned off and the current charges the output capacitor through the internal rectifier.
When the inductor current falls below the valley current limit value (nominally 600 mA), the low-side switch is turned on again, starting the next switching cycle. After the boost regulator output capacitor reaches approximately 6.0 volts, the peak and valley current limit levels are proportionally scaled down to approximately one fifth of their original values. When the boost regulator reaches its regulation limit (7.75 V typical), the low-side switch is turned off until the output voltage falls below the regulation limit again. The higher current limit values in the beginning of the boost regulator start-up sequence allow fast power up of the whole IC, while the normal operation with reduced current limit greatly reduces the switching noise and therefore improves the overall EMC performance. See Figure 12 for the boost regulator output voltage and inductor current waveforms (picture not to scale).
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
7.75V
Booster Output Voltage
Fault Timer t FAULT = 10 ms I pk Cu rrent Limit
t FAULT = 10 ms Ip k
6.0 V
0.5 I pk Retry Timer t Ret = 10 0 ms
0.5 Ipk
0A
0V
Ipk = 1 A typ.
Booster Inductor Current 0.6 A typ.
0.2 A typ. 0.1 A typ.
Figure 12. Boost Regulator Startup (Not To Scale)
SWITCHING REGULATOR
The switching regulator is a high-frequency (300 kHz default, adjustable in the range from 200 kHz to 400 kHz), synchronous buck converter driving integrated high-side and low-side N-channel power MOSFETs. The switching regulator output voltage is adjustable by means of an external resistor divider to provide the required output voltage within 2.0% accuracy, and is intended to directly power the core of the microprocessor. The buck controller uses a PWM Voltage Mode Control topology with Feed-Forward to achieve excellent line and load regulation. The 34702 integrated boost regulator provides a 7.75 V rail which is used to properly bias the switcher's MOSFET. In addition, the boost structure has a very low start up voltage (Typically 1.6 V), hence ensuring very low input voltage functionality. A typical bootstrap technique is used to provide voltage necessary to properly enhance the high-side MOSFET gate. When the regulator is supplied only from lowinput voltage (e.g., single +3.3 V supply rail), the bootstrap capacitor is charged from the internal boost regulator output VBST through an external diode. This arrangement allows the 34701 to operate from very low input voltage and also comply with the power sequencing requirements of the supplied microcontroller.
Figure 13. Switching Regulator Current Limit (Not To Scale) To avoid destruction of the supplied circuits, the switching regulator has a current limit with retry capability. When an overcurrent condition occurs and the switch current reaches the peak current limit value, the main (high-side) switch is turned off until the inductor current decays to the valley value, which is one-half of the peak current limit. If an overcurrent condition exists for 10 ms, the buck regulator control circuit shuts the switcher OFF and the switcher retry timer starts to time out. When the timer expires after 100 ms, the switcher engages the start-up sequence and runs for 10 ms, repeatedly checking for the overcurrent condition. Figure 13 describes the switching regulator overcurrent condition and current limit. During the current limited operation (e.g., in case of short circuit on the switching regulator output), the switching regulator operation is not synchronized to the oscillator frequency. Figure 14 (respectively Figure 15) depicts the current limit with a retry capability feature of the switcher (respectively LDO).
Figure 14. Switching Converter Overcurrent Protection
34701
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
retry timer starts to time out. When the timer expires after 100 ms, the LDO tries to power up again for 10 ms, repeatedly checking for the overcurrent condition. The current limit of the LDO can be set by using the following formula: ILIM = 50 mV/RS Where RS is the LDO current sense resistor, connected between the CS terminal and the LDO terminal output (see Figure 33 on page 32), and 50 mV is the typical value of the LDO current sense comparator threshold voltage. When no current sense resistor is used, it is still possible to detect the overcurrent condition by tying the current sense terminal CS to the VBST voltage. In this case, the overcurrent condition is sensed by saturation of the linear regulator driver buffer. The output voltage of the LDO can be adjusted by means of an external resistor divider connected to the feedback control terminal LFB. The linear regulator output voltage can be adjusted in the range of 0.8 V to VIN - LDO dropout voltage. Power-up, power-down, and fault management are coordinated with the switching regulator.
Figure 15. LDO Converter Overcurrent Protection The output voltage VOUT can be adjusted by means of an external resistor divider connected to the feedback control terminal INV. The switching regulator output voltage can be adjusted in the range of 0.8 V to VIN - buck dropout voltage. Power-up, power-down, and fault management are coordinated with the linear regulator.
POWER SEQUENCING VOLTAGE MARGINING WATCHDOG TIMER
A watchdog function is available via I2C bus communication. It is possible to select either window watchdog or time-out watchdog operation, as illustrated in Figure 16. Watchdog time-out starts when the watchdog function is activated via I2C bus sending a Watchdog Programming command byte, thus determining watchdog operation (window or time-out) and period duration (refer to Table 8, page 27). If the watchdog is cleared by receiving a new Watchdog Programming command through the I2C bus, the watchdog timer is reset and the new time-out period begins. If the watchdog time expires, the RST will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. After a watchdog time-out, the function is no longer active.
Watchdog Closed No Watchdog Clear Allowed 50% of Watchdog Period Watchdog Period Timing Selected via 12C Bus - See Table 4 Window Open for Watchdog Clear
SWITCHER OSCILLATOR
A 300 kHz (default) oscillator sets the switching frequency of the buck regulator. The frequency of the oscillator can be adjusted between 200 kHz and 400 kHz by an optional external resistor RF connected from the FREQ terminal of the integrated circuit to ground. See Figure 6 on page 14 for frequency resistor selection. The CLKSYN terminal can be configured as either an oscillator output when the CLKSEL terminal is left open or as a synchronization input when the CLKSEL terminal is grounded. The oscillator output signal is a square wave logic signal with 50% duty cycle, 180 degrees out-of-phase with the internal clock signal. This allows opposite phase synchronization of two 34702 devices. When the CLKSYN terminal is used as a synchronization input (CLKSEL terminal grounded), the external resistor RF chosen from the chart in Figure 6 should be used to synchronize the internal slope compensation ramp to the external clock. Operation is only recommended between 200 kHz and 400 kHz. The supplied synchronization signal does not need to be 50% duty cycle. Minimum pulse width is 1.0 s.
Window Watchdog
Window Open for Watchdog Clear
LOW DROPOUT LINEAR REGULATOR (LDO)
The adjustable low dropout linear regulator (LDO) is capable of supplying a 1.0 A output current. It has a current limit with retry capability. When the voltage measured across the current sense resistor reaches the 50 mV threshold, the control circuit limits the current for 10 ms. If the overcurrent condition still exists, the linear regulator is turned off and the
Watchdog Period Timing Selected via I2C Bus - See Table 4
Time-Out Watchdog Figure 16. Watchdog Operation
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
When the Window Watchdog function is selected, the timer cannot be cleared during the Closed Window time, which is 50% of the total watchdog period. When the watchdog is cleared, the timer is reset and starts a new time-
out period. If the watchdog is not cleared during the Open Window time, the RST will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES THERMAL SHUTDOWN
To increase the overall safety of the system designed with the 34701, an internal Thermal Shutdown function has been incorporated into the switching regulator circuit. The 34701 senses the temperature of the buck regulator main switching MOSFET (high-side MOSFET M1; see Figure 2 on page 2), the low-side (synchronous MOSFET M2), and control circuit. If the temperature of any of the monitored components exceeds the limit of safe operation (Thermal Shutdown), the switching regulator and the LDO shut down. After the temperature falls below the value given by the Thermal Shutdown hysteresis window, the switcher tries again to operate. The VOUT pulldown MOSFET M3 has an independent Thermal Shutdown control. If the M3 temperature exceeds the Thermal Shutdown, the M3 is turned off without affecting the switcher operation. The LDO pulldown MOSFET M4 has an independent Thermal Shutdown control. If the M4 temperature exceeds the Thermal Shutdown, the M4 will be turned off without affecting the LDO operation.
POWER SEQUENCING MODES
The power sequencing of the two outputs of this power supply IC is in compliance with the Freescale Power QUICC and other 32-bit microprocessor requirements. When the input voltage is applied, the switcher and linear regulator outputs follow the supply rail voltage during power-up and power-down in the limits given by the microcontroller power sequencing specification, illustrated in Figures 17 through 19. There are two possible power sequencing modes, Standard and Inverted, as explained in more detail below. The third mode of operation is Power Sequencing Disabled.
3.3 V Input 2.5 V
34701
VIN2 VBD VBST RT VIN1 LDRV CS LDO LFB 3.3 V
Other Circuits
VDDL (Core)
ADDR SDA SCL GND EN1 EN2 CLKSYN CLKSEL Optional FREQ
MCU RST BOOT SW VOUT PGND INV VDDI VBST 1.5 V VDDH (I/Os)
SOFT START
A switching regulator soft start feature is incorporated in the 34701. The soft start is active each time the IC is enabled, VIN is reapplied, or after a fault retry. Other transient events do not activate the soft start.
VOLTAGE MARGINING
The 34701 includes a voltage margining feature accessed through the I2C bus. Voltage margining allows for independent adjustment of the Switcher VOUT voltage and the linear output VLDO. Each can be adjusted up and down in 1.0% steps to a range of 7.0%. This feature allows for worst case system validation; i.e., determining the design margin. Margining details are described in the section entitled I2C Bus Operation, beginning on page 26 of this datasheet.
3.3 V Input Supply (I/O Voltage)
V = 2.1 V Max. Lead
1.8V Start-Up
1.5 V Core Voltage
Slope 1.0 V/ms
V = 2.1 V Max. Lead
V = 0.4 V Max. Lag
Figure 17. Standard Power Up/Down Sequence in +3.3 V Supply System
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
5.0 V Input
5.0 V Input
34701
VIN2 VBD VBST RT VIN1 LDRV CS LDO LFB MCU RST BOOT SW VOUT PGND INV VDDI Optional VBST 1.5 V VDDL (Core) 5.0 V 3.3 V VDDH (I/Os) VIN2 VBD VBST RT
34701
VIN1 LDRV CS LDO LFB MCU RST BOOT SW VOUT PGND INV VDDI VBST 3.3 V VDDH (I/Os) 1.5 V VDDL (Core)
ADDR SDA SCL GND EN1 5.0 V EN2 CLKSYN CLKSEL Optional FREQ
ADDR SDA SCL GND EN1 EN2 CLKSYN CLKSEL FREQ
V = 2.1 V Max. Lead V = 2.1 V Max. Lead
5.0 V Input Supply 3.3 V I/O Voltage (VLDO) 1.8V Start-Up 1.5 V Core Voltage (VOUT)
5.0 V Input Supply 3.3 V I/O Voltage (VOUT)
V = 2.1 V Max. Lead
V = 2.1 V Max. Lead
1.8V Start-Up
1.5 V Core Voltage (VLDO)
V = 0.4 V Max. Lag
V = 0.4 V Max. Lag
V = 0.4 V Max. Lag
V = 0.4 V Max. Lag
Figure 18. Standard Power Up/Down Sequence in +5.0 V Supply System
Figure 19. Inverted Power Up/Down Sequence in +5.0 V Supply System
ASSUMED REQUIREMENTS
1. I/O supply voltage not to exceed core voltage by more than 2.0 V. 2. Core supply voltage not to exceed I/O voltage by more than 0.4 V.
Methods of Control
STANDARD POWER SEQUENCING
When the power supply IC operates in the Standard Power Sequencing mode, the switcher output provides the core voltage for the microprocessor. This situation and operating conditions are illustrated in Figures 17 and 18. Table 5, page 16, shows the Power Sequencing mode selection.
INVERTED POWER SEQUENCING
When the power supply IC is operating in the Inverted Power Sequencing mode, the linear regulator (LDO) output provides the core voltage for the microprocessor, as illustrated in Figure 19. Table 5 shows the Power Sequencing mode selection.
The 34701 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. Power sequencing control is also achieved through the intrinsic operation of the regulators. The EN1 and EN2 terminals can be used to select the proper power sequencing mode required by the powered system or to disable the power sequencing (refer to Table 5).
Intrinsic Operation
For both the LDO and switcher, whenever the output voltage is below the regulation point, the LDO external Pass MOSFET is on, or the Buck High-Side MOSFET is on at a duty cycle controlled by the switcher. Because these devices are MOSFETs, current can flow in either direction, balancing the voltages via the common supply terminal. The ability to maintain the MOSFETs on is dependent on the available gate voltage, and thus the size of the boost regulator storage capacitor.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Standard Power Sequencing Control
Comparators monitor voltage differences between the LDO (LDO terminal) and the switcher (VOUT terminal) outputs as follows: 1. LDO > VOUT + 1.9 V, turn off LDO. The LDO can be forced off. This occurs whenever the LDO output voltage exceeds the switcher output voltage by more than 1.9 V. 2. LDO > VOUT + 2.0 V, shunt LDO to ground. If turning off the LDO is insufficient and the LDO output voltage exceeds the switcher output voltage by more than 2.0 V, a 1.5 shunt MOSFET is turned on that discharges the LDO load capacitor to ground. The shunt MOSFET is used for switcher output shorts to ground and for power down in case of VIN1 VIN2 with the switcher output falling faster than the LDO. 3. LDO < VOUT + 1.9 V cancel (2). 4. LDO < VOUT + 1.8 V, cancel (1) above, re-enable LDO. Normal operation resumes when the LDO output voltage is less than 1.8 V above the switcher output voltage. 5. LDO < VOUT - 0.1 V, turn off switcher. The switcher can be forced off. This occurs whenever the LDO is less than VOUT - 0.1 V. 6. LDO < VOUT - 0.3 V, turn on Sync (LS) MOSFET and 1.5 VOUT sink MOSFET. The Buck High-Side MOSFET is forced off and the Sync MOSFET is forced on. This occurs when the switcher output voltage exceeds the LDO output by more than 300 mV. 7. LDO > VOUT - 0.3 V, cancel (6). 8. LDO > VOUT - 0.1 V, cancel (5). Normal operation resumes when LDO < VOUT - 0.1 V.
Inverted Power Sequencing Control
VOUT output voltage is less than 1.8 V above the LDO output voltage. 4. VOUT < LDO + 2.0 V, cancel (2) 5. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be forced off. This occurs whenever the VOUT is less than VLDO - 0.2 V. 6. VOUT < LDO - 0.3 V, turn on the 1.5 LDO sink MOSFET. This occurs when the LDO output voltage exceeds the VOUT output by more than 300 mV. 7. VOUT < LDO - 0.2 V, cancel (6). 8. VOUT < LDO - 0.1 V, cancel (5). Normal operation resumes when VOUT > LDO - 0.1 V.
STANDARD OPERATING MODE
Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the switcher supplies core voltage (e.g., 1.5 V nominal), and the LDO operates independently (see Figure 17, page 21). Power sequencing depends only on the normal switcher intrinsic operation to control the Buck High-Side MOSFET.
Power-Up
When VIN is rising, initially VOUT is below the regulation point and the Buck High-Side MOSFET is on. In order not to exceed the 2.1 V differential requirement between the I/O (VIN) and the core (VOUT), the switcher must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for VIN is 1.0 V/ms.
Power-Down
Comparators monitor voltage differences between the switcher (VOUT terminal) and LDO (LDO terminal) outputs as follows: 1. VOUT > LDO + 1.8 V, turn off VOUT . The switcher VOUT can be forced off. This occurs whenever the VOUT output voltage exceeds the LDO output voltage by more than 1.8 V. 2. VOUT > LDO + 2.0 V, shunt VOUT to ground. If turning off the switcher VOUT is insufficient and the VOUT output voltage exceeds the LDO output voltage by more than 2.0 V, a 1.5 shunt MOSFET and the switcher synchronous MOSFET are turned on to discharge the VOUT load capacitor to ground. The shunt MOSFET and synchronous MOSFET are used for LDO output shorts to ground and for power-down in case of VIN1 VIN2 with LDO output falling faster than the VOUT. 3. VOUT < LDO + 1.8 V, cancel (1) and (2) above, reenable VOUT . Normal operation resumes when the
When VIN is falling, VOUT falls below the regulation point; therefore, the Buck High-Side MOSFET is on. In the case where VOUT is falling faster than VIN, the Buck High-Side MOSFET attempts to maintain VOUT. In the case where VIN is falling faster than VOUT, the Buck High-Side MOSFET is also on, and the VOUT load capacitor is discharged through the Buck High-Side MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (VOUT) does not exceed the I/O voltage (VIN) by more than a maximum of 0.4 V.
Shorted Load
1. VOUT shorted to ground. This causes the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. 2. VIN shorted to ground. Until the switcher load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the switcher, the load capacitor is discharged rapidly through the Buck High-Side MOSFET to VIN. 3. VOUT shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown.
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 VIN2
The LDO supplies the microprocessor I/O voltage. The switcher supplies the core (e.g., 1.5 V nominal) (see Figure 18, page 22).
Power-Up
1. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the section Methods of Control on page 22. In the case VIN1 = VIN2, the intrinsic operation turns on both the Buck High-Side MOSFET and the LDO external Pass MOSFET, and discharges the LDO load capacitor into the VIN supply. 2. LDO falls faster than VOUT . The switcher uses control methods (5) and (6) described in the section Methods of Control on page 22.
Shorted Load
This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: 1. LDO rises faster than VOUT. The LDO uses control methods (1) and (2) described in the section Methods of Control on page 22. 2. VOUT rises faster than LDO. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 22.
Power-Down
1. VOUT shorted to ground. The LDO uses method (1) and (2) described in the section Methods of Control on page 22. 2. LDO shorted to ground. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 22. 3. VIN1 shorted to ground. Device is not working. 4. VIN2 shorted to ground with VIN1 and VIN2 different. This is equivalent to the switcher output shorted to ground. 5. VOUT shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown. 6. LDO shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown.
This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases:
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
INVERTED OPERATING MODE
Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V
Power-Up
The 3.3 V supplies the microprocessor I/O voltage, the LDO supplies core voltage (e.g., 1.5 V nominal), and the switcher VOUT operates independently. Power sequencing depends only on the normal LDO intrinsic operation to control the Pass MOSFET.
Power-Up
This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: 1. VOUT rises faster than LDO. The switcher VOUT uses control methods (1) and (2) described in the section Methods of Control on page 22. 2. LDO rises faster than VOUT . The LDO uses control methods (5) and (6) described in the section Methods of Control on page 22.
Power-Down
When VIN is rising, initially LDO is below the regulation point and the Pass MOSFET is on. In order not to exceed the 2.1 V differential requirement between the I/O (VIN) and the core (LDO), the LDO must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for VIN is 1.0 V/ms.
Power-Down
This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases: 1. LDO falls faster than VOUT . The VOUT uses control methods (4) and (5) described in the section Methods of Control on page 22. In the case VIN1 = VIN2, the intrinsic operation turns on both the Buck High-Side MOSFET and the LDO external Pass MOSFET, and discharges the VOUT load capacitor into the VIN supply. 2. VOUT falls faster than LDO. The LDO uses control methods (5) and (6) described in the section Methods of Control on page 22.
Shorted Load
When VIN is falling, LDO falls below the regulation point; therefore, the Pass MOSFET is on. In the case where LDO is falling faster than VIN, the Pass MOSFET attempts to maintain LDO. In the case where VIN is falling faster than LDO, the Pass MOSFET is also on, and the LDO load capacitor is discharged through the Pass MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (LDO) does not exceed the I/O voltage (VIN) by more than maximum of 0.4 V.
Shorted Load
1. LDO shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. 2. VIN shorted to ground. Until the LDO load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the LDO, the load capacitor is discharged rapidly through the Pass MOSFET to VIN. 3. LDO shorted to supply. No load protection.
Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 VIN2
1. LDO shorted to ground. The VOUT uses methods (1) and (2) described in the section Methods of Control on page 22. 2. VOUT shorted to ground. The LDO uses control methods (5) and (6) described in the section Methods of Control on page 22. 3. VIN1 shorted to ground. Device is not working. 4. VIN2 shorted to ground. This is equivalent to the switcher VOUT output shorted to ground. 5. LDO shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown. 6. VOUT shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown.
The switcher VOUT supplies the microprocessor I/O voltage. The LDO supplies the core (e.g., 1.5 V nominal) (see Figure 19, page 22).
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS I2C BUS OPERATION
The 34701 device is compatible with the I2C interface standard. SDA and SCL terminals are the Serial Data and Serial Clock terminals of the I2C bus.
Table 6. Definition of Selectable Portion of Device Address
ADDR Terminal Low High (Open) Low High (Open) A1 0 0 1 1 A0 0 1 0 1
CLKSEL Terminal Low Low High (Open) High (Open)
I2C COMMAND AND DATA FORMATS
Communication Start
Communication starts with a START condition, followed by the slave device unique address. The Read/Write (R/W) bit defines whether the data should be read from or written to the device (the 34701 operates only as a slave device; therefore, the R/W bit should always be set to 0). The 34701 responds by sending the Acknowledge bit (Ack) to the master device. Figure 20 illustrates the beginning of an I2C communication for a 7-bit slave address.
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA can be written into the slave registers. The R/W bit must be set to 0 to allow DATA to be written into the 34702. Figure 22 shows the data write sequence. Actions performed by the slave device are grayed.
S 7-Bit Address 0 Ack DATA Ack
S
7-Bit Address
R/W
Ack
Figure 20. Communication Start Using 7-Bit Address Slave Address Definition
(Write)
Figure 22. Data Transfer for Write Operations DATA Definition
34701 has the two least significant address bits (LSB) defined by the state of the CLKSEL terminal (A1) and the ADDR terminal (A0). Note The state of the CLKSEL terminal also defines the configuration of the oscillator synchronization CLKSYN terminal. Leaving the CLKSEL terminal open or pulling it high defines the CLKSYN terminal as an oscillator output. When the CLKSEL terminal is pulled low, the CLKSYN terminal is configured as a synchronization input for the external clock signal. This feature allows up to four 34701 ICs to communicate in the same I2C bus, all of them sharing the same high-order address bits. A different combination of the two LSB address bits A1 and A0 can be assigned to each individual part to assure its unique address. Figure 21 illustrates the flexible addressing feature for a 7-bit address. Table 6 provides the definition of the selectable portion of the device address. When the ADDR terminal is used and put to low level, pull the ADDR terminal to ground through a 10 k resistor.
MSB
The DATA field in the single Data Transfer contains one or several Command Bytes. The Command Byte identifies the kind of operation required by the master to be performed and has two fields, as illustrated in Figure 23: 1. Address field 2. Value field The address field is selected from the list in Table 7.
MSB
Bits 6 5 4 3 2 1
LSB
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Address Field Value Field
Figure 23. Command Byte Table 7. Address Field Definitions
Operation Voltage Margining Watchdog Write W W
Bits 5 1 4 1 32 0 1
LSB
Address Field 001 011
6 1
0
1 A1 A0
Fixed Address Selectable Address
Figure 21. Address Bit Definition for 7-Bit Address
Refer to Table 8, page 27, which summarizes the value field definitions for the entire set of operation options.
34701
26
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Table 8.
Command Byte Definitions
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 Value 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 Action 1st Command Output Nominal + 1.0% + 2.0% + 3.0% + 4.0% + 5.0% + 6.0% + 7.0% - 1.0% - 2.0% - 3.0% - 4.0% - 5.0% - 6.0% - 7.0% 1st Command WD OFF
(23)
Security in Writing Commands
Operation Voltage Margining (As a 2nd Command Byte)
To improve the security level, a so-called first command is defined to initiate each write communications. The first command identifies the operation, which is executed by the following Command Byte. A first command has the address field equal to the related operation one, followed by a null value field (all zeros). Table 9 summarizes first command definitions. The master sends the first command before the Command Byte for the intended operation.
Table 9. First Command Definitions
Operation Voltage Margining Watchdog Programming
LDO Output: x=0
Switcher Output
0 0 0 0 0 0 0 0 0 0
First Command 001 00000 011 00000
x=1
VOLTAGE MARGINING OPERATION
After starting the communication in Writing mode, the master sends the first command followed by the specific Command Byte to set the required voltage margining for either the LDO or the switcher (see Figure 24). To achieve a simultaneous set for both LDO and switcher, two specific commands must be issued in sequence after the first command, one for each supply.
0 0 1 0 0 0 0 0 Ack 0 0 1 x x x x x First Byte for Voltage Margining Command Byte
Watchdog Programming (As a 2nd Command Byte)
0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
WD 1280 ms Wind. OFF WD 320 ms Wind. OFF WD 80 ms Wind. OFF WD 20 ms Wind. OFF WD 1280 ms Wind. ON WD 320 ms Wind. ON WD 80 ms Wind. ON WD 20 ms Wind. ON
Figure 24. Voltage Margining Programming (One Supply Only) Note: x bits, which set the voltage margining value are defined in Table 8.
WATCHDOG PROGRAMMING OPERATION
For watchdog operation control, the master periodically sends a watchdog first command followed by a command byte selecting, or confirming, the watchdog period according to the options listed in Table 8. See Figure 25 for the watchdog timer programming command example. The internal watchdog timer is turned ON by receiving a valid Watchdog Programming command (after receiving the Watchdog Programming First Command), and it is cleared each time the next Watchdog Programming command is written into the device, provided it arrives during the window open time. Thus, the Watchdog Programming command clears the timer and sets the new timing conditions at the same time. The Watchdog Programming First Command 01100000 sent twice shuts the timer OFF, and the watchdog function is disabled. Any other valid watchdog command turns the timer ON again.
Notes 23. The Watchdog timer is turned ON automatically after receiving any other valid command byte changing watchdog time.
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
27
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
S A6 A5 A4 A3 A2 A1 A0 0 Ack
0 1 1 0 0 0 0 0 Ack 0 1 1 x x x x x First Byte for Watchdog Programming Command Byte
START Slave Address Write
Figure 25. Watchdog Timer Programming Note: x bits, which set the watchdog timer value are defined in Table 8, page 27. Communication Stop
0
0
1
0
0
0
0
0 Ack
First Command for Voltage Margining
0
0
1
0
0
1
0
1 Ack P STOP
Only the master can terminate the data transfer by issuing a STOP condition. The slave waits for this condition to resume its initial state waiting for the next START condition (see Figure 26).
Address Field Value Field = LDO 5th Setting
Figure 27. Data Transfer Example - LDO Voltage Margining
COMPLETE DATA TRANSFER EXAMPLES
The master device controlling the I2C bus always starts addressing a 34701 slave IC in writing mode (R/W = 0) to enable it to write a Command Byte just after receiving the address acknowledge sent by 34702. I2C bus protocol defines this circumstance as a master-transmitter and slavereceiver configuration. Figure 27 illustrates a communication beginning with the slave address, the first command for voltage margining, and a third byte containing the address field 001 and the value field 00101 corresponding with the LDO fifth setting (LDO output voltage = +5% above its nominal value). If a simultaneous setting for switcher is needed, a fourth byte should be included before the STOP condition (P); for instance, 001 11100 to set the switcher in its twelfth setting (switcher output voltage = -5% below its nominal value) - see Figure 28. The example of data transfer setting the Watchdog timer is shown in the Figure 26.
S A6 A5 A4 A3 A2 A1 A0 0 Ack
START Slave Address Write
0
0
1
0
0
0
0
0 Ack
First Command for Voltage Margining
0
0
1
0
0
1
0
1 Ack
Address Field Value Field: LDO VLDO = Nom. + 5% 0 0 1 1 1 1 0 0 Ack P
STOP Address Field Value Field: Switcher VOUT = Nom. - 5%
Figure 28. Data Transfer Example - LDO and Switcher Voltage Margining
S A6 A5 A4 A3 A2 A1 A0 0 Ack
START Slave Address Write
0
1
1
0
0
0
0
0 Ack
First Command for Watchdog Programming
0
1
1
0
1
0
0
1 Ack P
STOP Address Field Value Field: Time-out WD = 320 ms (Window OFF)
Figure 26. Data Transfer Example - Watch Dog Timer Setting.
34701
28
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATION
TYPICAL APPLICATION
BUCK REGULATOR CONTROL CIRCUIT
The 34701 buck regulator utilizes a PWM Voltage Mode topology with Feed-Forward to achieve an excellent line and load regulation. The control circuit block diagram is shown in Figure 29.
L
Figure 29. Buck Regulator Control Circuit The integrated 40 pF capacitor CF charged through the Vm1 is the ramp generated by the internal ramp generator (Vm1 = 0.5 V typ.). external resistor R4 provides the feed-forward ramp . waveform, the amplitude of which is proportional to the input voltage, thus providing the feed-forward function. G ain [dB] Figure 30 shows the Bode plot of the 34701 buck regulator 20 fLC control loop gain and phase versus frequency. fz(c) The first double pole on the Bode plot is created by the buck regulator output L-C filter, and its frequency can be f BW 0 calculated as: fz(E SR) fp (FF) 1 f LC = ---------------------2 C O L
fp(c)
-20
Where CO is the value of the buck output capacitor and L is the inductance value of the output filter inductor L. The frequency of the compensating zero can be calculated as follows.
fz ( c ) 1 = --------------------------------------2C2 ( R1 + R3 )
-40 -180 Pha se [Deg.]
The Feed-Forward implemented by resistor R4 and integrated capacitor CF creates a pole in the overall loop transfer function, the frequency of which can be calculated from the following formula.
V IN 1f p ( FF ) = --------------------------------------------------------------- x -------------------( V IN - V Ref ) 2R4C F 1 ------- x ------------------------------- + V m1 R4C F f sw
-2 70
m
Where VRef is the buck regulator reference voltage (VRef = 0.8 V typ.) at the INV terminal, VIN is the buck regulator input voltage,
-3 60 1.0
10
100
10 00 Frequency [k Hz ]
10000
Figure 30. Buck Control Loop Bode Plot
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
29
TYPICAL APPLICATION
The frequency of the zero created by the ESR of the output capacitor CO is calculated as:
1 f z ( ESR ) = ------------------------2C O ESR
RU is the "upper" resistor of the LDO resistor divider, RL is the "lower" resistor of the LDO resistor divider. Figure 31 describes the 34701 linear regulator circuit with the resistor divider RU, RL setting the output voltage VLDO.
2.8 V to 6.0 V Input MC34701 VIN1
Where CO is the value of the buck regulator output capacitor, and ESR is the equivalent series resistance of the output capacitor. The frequency of the compensating network pole can be calculated as follows:
LDRV
fp ( c )
1 = ---------------------------------------R1R3 2C2 ------------------------( R1 + R3 )
CS LDO LFB LCMP
RS RU RL
VLDO CLDO
The well designed and compensated buck regulator should yield at least 45 deg. phase margin m of its overall loop as depicted in the Figure 30, page 29.
Selecting Buck Regulator Output Voltage
LDO Compensation
The 34701 buck regulator output voltage can be set by selecting the right value of the resistors R1, R2 and R4, and can be determined from the following formula (see Figure 29, page 29 for the component references):
1 R2 = V Ref x ---------------------------------------------------------------------------------------( V O + I O x R L ) - V Ref V O - V Ref ------------------------------------------------------- + ------------------------R4 R1
Figure 31. 34701Linear Regulator Circuit Linear Regulator Current Limit
Where VRef is the buck regulator reference voltage (VRef = 0.8 V typ.) at the INV terminal, VO is the selected output voltage, IO is the output load current, RL is the DC resistance of the inductor L. It is apparent that the buck regulator output voltage is affected by the voltage drop caused by the inductor serial resistance and the regulator output current. In those applications which do not require precise output voltage, setting the formula for calculating selected output voltage can be simplified as follows:
1 R2 = V Ref x -------------------------------------------------------------( R1 + R4 ) ( V O - V Ref ) x ------------------------R1 x R4 Linear Regulator Output Voltage
As described in the Linear Regulator Functional Description section, the current limit of the linear regulator can be adjusted by means of an external current sense resistor RS. The voltage drop caused by the regulator output current flowing through the current sense resistor RS is sensed between the LDO and the CS terminals. When the sensed voltage exceeds 50 mV (typical), the current limit timer starts to time out while the control circuit limits the output current. If the overcurrent condition lasts for more than 10 ms, the linear regulator is shut off and turned on again after 100 ms. This type of operation provides equivalent protection to the analog "current foldback" operation. It is important to keep in mind that the amount of capacitive load which can be supplied by the by the linear regulator is limited by the setting of the LDO current limit. During the power-up period, the linear regulator operates in the current limit, supplying the current into the load of the LDO, which includes all the capacitors connected to the regulator output. If the total amount load is so large that the regulator could not reach its regulation voltage in 10 ms during the power-up, it turns off and tries to power up again after 100 ms. This situation may lead to the power-up oscillations.
Linear Regulator External MOSFET
The output voltage of the linear regulator (LDO) can be set by a simple resistor divider according to the following formula:
RU V LDO = V Ref x 1 + ------ RL
Where VRef is the linear regulator reference voltage (VRef = 0.8 V typ.) at the LFB terminal, VLDO is the LDO selected output voltage,
The linear regulator uses an external N-channel power MOSFET to provide a pass element for the power path. The selection of the proper type of the external power MOSFET is critical for optimum performance and safe operation of the linear regulator. The power MOSFET's threshold voltage, RDS(on), gate charge, capacitances and transconductance are important parameters for the stable operation of the linear regulator while the package of the power MOSFET determines the
34701
30
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATION
maximum power dissipation, and hence the maximum output current for the required input-to-output voltage drop. The power dissipation of the external MOSFET can be calculated from the simple formula:
P D ( Q ) = I LDO x ( V IN - V LDO )
Where PD(Q) is the power MOSFET power dissipation VIN is the LDO input voltage, VLDO is the LDO output voltage, ILDO is the LDO output load current. Table 10 shows the recommended power MOSFET types for the 34701 linear regulator, their typical power dissipation, and thermal resistance junction-to-case.
Table 10. Recommended Power MOSFETs
Part No. IRL2703S MTD20N03HDL Package D2PAK DPAK Typ. PD 2.0 W 1.75 W* RthJ-C 3.3 C/W 1.67 C/W
NOTE: Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in figures or tables. Although Freescale offers component recommendations, it is the customer's responsibility to validate their application. *When mounted to an FR4 using 0.5 sq.in. drain pad size
significantly improves regulation parameters and electromagnetic compatibility (EMC) performance of the switching regulator, poor layout practices can lead not only to significant degradation of regulation and EMC parameters but even to total dysfunction of the whole regulator IC. Extreme care should be taken when laying out the ground of the regulator circuit. In order to avoid any inductive or capacitive coupling of the switching regulator noise into the sensitive analog control circuits, the noisy power ground and the clean quiet signal ground should be well separated on the printed circuit board, and connected only at one connection point. The power routing should be made by heavy traces or areas of copper. The power path and its return should be placed, if possible, atop each other on the different layers or opposite sides of the PC board. The switching regulator input and output capacitors should be physically placed very close to the power terminals (VIN2, SW, PGND) of the 34701 switching regulator; and their ground terminals, together with the 34701 power ground terminals (PGND), should be connected by a single island of the power ground copper to create the "single-point" grounding. Figure 32 illustrates the 34701 switching regulator grounding concept. The bootstrap capacitor Cb should be tightly connected to the integrated circuit as well.
BOOT Cb VIN2 SW
VBST
Vin = 5.0 V
The maximum power dissipation is limited by the maximum operating junction temperature TJmax. The allowed power dissipation in the given application can be calculated from the following expression:
T Jmax - T A P D ( Q )max -------------------------------------------------------R thJC + R thCB + R thBA
Vout = 1.5 V
To Load
INV
Where PD(Q)max is the power MOSFET maximum allowed dissipation, TJmax is the power MOSFET maximum operating junction temperature, TA is the ambient temperature, RthJC is the power MOSFET thermal resistance junction-to-case, RthCB is the thermal resistance case-to-board, RthBA is the thermal resistance board-to-ambient of the PC board.
PCB Layout Considerations
Vout Return
PGND GND Power Ground Signal Ground
As with any power application, the proper PCB layout plays a critical role in the overall power regulator performance. While good careful printed circuit board layout
Figure 32. 34701 Buck Regulator Layout The same guidelines as those for the layout of the main switching buck regulator should be applied to the layout of the low power auxiliary boost regulator and to some extent, the power path of the linear regulator.
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
31
TYPICAL APPLICATION
+3.3V Supply Voltage
VIN1 CIN 10uF VBST CBST 10uF 10uH LBST VBD 8.0V
VIN VDDI Internal Supply VBST Power Enable VDDI Bandgap Voltage Reference VDDI VDDI Linear Regulator Control I-lim VDDI VDDI 1.0 uF
VBST LDRV CS LDO
7.75V
+ Reset SysCon INV LFB Vref
QLDO RS 0.022 R
Q5
Boost Control
Vref Vref
VLDO=3.3V @1.0A
CLDO 5 x 2.2 uF
Vref
+3.3V or VLDO
5.1k
LFB
4.7k 1.5k
EN1 EN2 Power Sequencing Reset Control POR Timer Voltage Margining W-dog Timer
VLDO Power Down VOUT
Pow. Seq. UVLO VBST
Q4 VBST
LCMP 100pF
1.5k 6.8nF
RST to MCU
RST RESET
Q6
RT Rt 100k Ct 100nF
BOOT VIN2 (2)
VBST
Current Limit I2C Control SysCon VDDI Buck HS & LS Driver
Q1
I2C Control
CIN 2 x 22 uF SW CB DB 0.1uF
+3.3V Supply Voltage
L1 4.7 uH
Thermal Limit
SoftSt
ADDR Rpd 10k SDA SCL I2C Interface Switcher Oscillator 300kHz Ramp Gen.
Buck Control Logic
VOUT=1.8V
+ CO 100 uF
Q2
(2) PGND
300k
PWM Comp. + -
Error Amp.
+ -
0.8V
To Reset Control
(2) INV 39k 27k Rb
VOUT Pow. Seq. Q3 VOUT
300
470pF
CLKSEL
CLKSYN
FREQ RF (Optional)
(4) GND
Figure 33. Simplified Block Diagram and Basic Application
34701
32
Analog Integrated Circuit Device Data Freescale Semiconductor
VIN2
U6 VIN1 1 FREQ CLKSYN R11 0.022R LDO LFB 27 28 EN1 EN2 LCMP 1.5k 6.8nF C34 10nF /RESET RT BOOT 2 VBD VBST SW SW 6 7 13 C40 R18 4.7nF 2.2R VBD 12 C15 100nF R4 10k 1 14 BOOT L1 4.7uH R10 300k 2 C10 + 100uF C17 470pF R9 300R R12 R8 39k C14 10nF R19 510R 1 VOUT 29 C7 33nF 30 VIN2 C3 C37 10uF + C39 1.0uF VIN2 VIN2 17 LCMP VCC5V VIN 1 + C36 1.0uF L3 3.3uH 1 2 RLF7030-3R3M4R1 4 5 100uF L2 1 10uH SLF6025T C33 10uF/16V PGND PGND CLKSEL ADDR GND GND GND GND VDDI VOUT 3 INV 2 31 26 23 C18 1.0uF 8 9 24 25 MC34701 10 11 C2 10uF R17 C35 18 19 R13 4.7k C23 10uF CS 20 CS LDRV 32 15 16 SDA SCL 21 LDRV Q1 IRL2703S or MTD20N03HDL R1 10k 1 1 1 1 22 C16 1.0uF
CLKSY N SDA SCL GND
NOTES: 1. R11 can be adjusted according to the required LDO current limit. 2. R12 = 16K for Vout = 2.5V R12 = 27K for Vout = 1.8V. R12 = 36K for Vout = 1.5V. 3. L1 = 4.7uH, DO3316P-472HC from Coilcraft or CDRH104R-4R7 from Sumida. 4. L2 = 10uH, SLF6025T-100M1R3 from TDK or 1812PS-103M from Coilcraft. 5. L3 = 3.3uH, RLF7030-3R3M4R1 from TDK 6. C2 = 10uF/10V, ceramic capacitor . 7. C3, C10 = 100uF/6.3V, 10THB100ML POSCAP capacitor from Sanyo.
BOOT
Analog Integrated Circuit Device Data Freescale Semiconductor
3.3V
R2 1 VLDO
5 x 2.2 uF
R15 1.5k
5.1k
1
RESET
C37, L3 Optional
C40, R18 Optional
D2 LL4148
Figure 34. 34701 Typical Application Circuit
Signal ground
Power ground
TYPICAL APPLICATION
34701
33
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
Important: For the most current package revision, visit www.freescale.com and perform a "keyword" search for the "98A" number.
10.3 7.6 7.4 C 5
1 32
B 9
2.65 2.35
30X
0.65
PIN 1 ID 4 B B 9 11.1 10.9 C L
16
17
5.15
2X 16 TIPS
A
32X
SEATING PLANE
0.3
A
B
C A (0.29) 0.25 0.19 A
BASE METAL
0.10 A
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
SECTION A-A ROTATED 90_ CLOCKWISE
34701
34
CEE E CCCC EEE CCCC CCC
6 0.38 0.22 0.13
M
(0.203)
R0.08 MIN 0.25
GAUGE PLANE
PLATING
MIN
0
0.29 0.13
CA
M
B
8 8 0 0.9 0.5 SECTION B-B
98AARH99137A
CASE 1324-02 ISSUE A
Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
NOTES
34701
Analog Integrated Circuit Device Data Freescale Semiconductor
35
PACKAGE DIMENSIONS
34701
36
Analog Integrated Circuit Device Data Freescale Semiconductor
How to Reach Us:
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MC33701 Rev 4.0 05/2005
PACKAGE DIMENSIONS
34701
38
Analog Integrated Circuit Device Data Freescale Semiconductor

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